Hardware Design using Digital Components and Its Implementation on FPGA For SF 54, 56 & 57
Foundation_Course_Digital_Hardware_Design_For_Electronics & Electricals_Engineering__2023_2024
Program objective of Project-based Learning cum Internship Program in VLSI: –
1. Understanding Hardware Design of VLSI & Embedded Domain
2. Hands-on Experience Design and
3. Optimization Techniques
4. Industry-Relevant Skills
5. Project Development
6. Networking and Industry Exposure
Summary of the program:-
1. Introduction of VLSI & Embedded flow
2. From this training, trainees can identify the interest area in VLSI & Embedded
3. 100% hands-on session from the first day of the learning
4. Focus on Major and minor project-based internship
5. From this training, students can identify their final-year project
6. Tools and Hardware board will be provided by the academy only
Key takeaways from the training program: –
1. How to develop the logical approach using digital components in hardware design and Implementation of FPGA
2. Hardware Circuit design using digital components of Real-time applications like signed calculator, multiplier,
divider, digital clock, stopwatch timer, and LED blinker.
3. Understanding of FPGA Architecture from Idea to programming in both hardware design and HDL- Verilog
What Will I Learn?
- 1. How to develop the logical approach using digital components in hardware design and Implementation of FPGA
- 2. Hardware Circuit design using digital components of Real-time applications like signed calculator, multiplier,
- divider, digital clock, stopwatch timer, and LED blinker.
- 3. Understanding of FPGA Architecture from Idea to programming in both hardware design and HDL- Verilog
Course Content
Hardware System Design – Combination
-
How to develop the logic using the digital concept -1.
50:11 -
How to develop the logic using the digital concept -2.
50:02 -
Introduction to Adder
50:06 -
Introduction of Subtractor and Tool
59:10 -
Introduction of Full Subtractor
01:04:25 -
Digital Multiplexer Part 1
57:30 -
Digital Mux Part 2
50:30 -
Tool Demo
01:27:34 -
Demux and Introduction of 2’s complement
53:27 -
2s Complement & Sign Calculator Project
33:40 -
How to design the multiple bits on input and outputs nodes
23:17 -
Encoder & Decoder Learning & Design
46:16 -
Multiple bits on single line – Another example
36:56 -
4_Bit Adder,2_1 Demux BUS Design
01:17:10 -
Signed Multiplier Part
01:18:07 -
Digital_L4_SFF_11th_July_24 Divider
01:31:36 -
Digital_L4_SFF_12th_July_24
58:57 -
SF 57 Encoder Decoder Multiplier
01:46:26 -
Doubt Session SF 57_56_54
01:06:04
Digital Design Verilog
Sequential Design
About the instructor
9 Courses
439 students