Vaibhav Mishra

July 25, 2024

Hardware Design using Digital Components and Its Implementation on FPGA for SF 47 , SF 48, SF 49 , SF 50

5.002

103 Enrolled

Foundation in VLSI

Foundation_Course_Digital_Hardware_Design_1 st & 2nd_Year_Electronics & Electricals_Engineering__2023_2024

Program objective of Project-based Learning cum Internship Program in VLSI: –
1. Understanding Hardware Design of VLSI & Embedded Domain
2. Hands-on Experience Design and
3. Optimization Techniques
4. Industry-Relevant Skills
5. Project Development
6. Networking and Industry Exposure

Summary of the program:-
1. Introduction of VLSI & Embedded flow
2. From this training, trainees can identify the interest area in VLSI & Embedded
3. 100% hands-on session from the first day of the learning
4. Focus on Major and minor project-based internship
5. From this training, students can identify their final-year project
6. Tools and Hardware board will be provided by the academy only

Key takeaways from the training program: –
1. How to develop the logical approach using digital components in hardware design and Implementation of FPGA
2. Hardware Circuit design using digital components of Real-time applications like signed calculator, multiplier,
divider, digital clock, stopwatch timer, and LED blinker.
3. Understanding of FPGA Architecture from Idea to programming in both hardware design and HDL- Verilog

What Will I Learn?

1. How to develop the logical approach using digital components in hardware design and Implementation of FPGA
2. Hardware Circuit design using digital components of Real-time applications like signed calculator, multiplier,
divider, digital clock, stopwatch timer, and LED blinker.
3. Understanding of FPGA Architecture from Idea to programming in both hardware design and HDL- Verilog

Course Content

|| Hardware design || Brainstorming Session 1 & 2 || Tool Demo
During the lecture, we learned about the following topics: 1. The process of designing all six gates by utilizing universal NAND and NOR gates. 2. How to design circuits using any gates and universal gates. 3. A demonstration of the XILINX ISE Schematics tool. 4. An overview of the sign calculator project.

Brainstorming session 1 & 2 || Designing of gates || Tool Demo

01:15:35

Hardware Design – Designing of Adder and Its application.
In this video, we have covered 1. Basis of HA 2. How HA and FA are different from each other 3. Designing of HA using Universal gate 4. Challenge in HA

Digital Multiplexer
In this lecture , we have covered the 1. Introduction of Mux 2. Internal Circuits of Mux 3. Why Mux is universal components 4. Design of different gates using Mux

Tool Demo
Tool Demo - How to use the tool Xilinx for Hardware Design

Demux and Its Application
In this session, we have covered the internal workings of demux and how we can design 1:8 demux using 1:2 demux and also discussed how to design different gates with 1:2 demux.

2s Complement and Project Sign Calculator
We have discussed how the 2s complement is working in the Sign Calculator Project

How to use the Multiple bits on the multiple inputs and outputs
Bus and Tap is one of the tool features, Which helps the designer to implement multiple bits on inputs and multiple outputs

Hardware Design of Multiplier and Design
Schematics Design of 4 bit Multiplier and its implementation

Encoder & Decoder Learning & Design
Learn how to design the encoder and decoder internal circuit and how this is going to use in the sign calculator design

Hardware Design of Digital Divider Circuit
How to design the digital divider circuit both sign and unsigned and implementation on FPGA

Hardware Design using Verilog

Verilog : Introduction of gate level with example
What is gate level, where is it used, and what is the importance of gate level in Verilog?

Verilog Gate Level 2 || How Gate Level help to design Sign Calculator || Introduction of Operator
How to design the different components of a sign calculator How to connect the different components Introduction of Operator, types of operator What is a logical operator

Verilog Operator Class
Logical Operator Reduction Operator Bitwise Operator

Verilog Operator
Reduction Bitwise Shift Relational Equality Airthmatics Conditional

Sequential_Design
Theory of Sequential Logic Design

Sequential Gated Latch and Importance of X & Z

Sequential Gated Latch and Bug

SR bug Solved JK Failed and MS JK
SR bug Solved JK Failed and MS JK

Edge Based Circuit Using MS JK FF
What is an edge-based circuit What is level based circuit How the FF is working edge How Nand and Nor decide Rising and Falling edge What is positive edge and negative edge

DFF & TFF
What is DFF and TFF What is the truth table of both DFF and TFF Application of DFF & TFF Internal Circuit of the DFF & TFF

Verilog – Behavioral Modelling
Initial and Always Blocking and Non-Blocking

About the instructor

Vaibhav Mishra

5.00 (3 ratings)

7 Courses

230 students

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PinE Training Academy 6 months ago

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Durations: 50 hours

Lectures: 37

Students: Max 0

Level: Expert

Language: English

Certificate: Yes

Material Includes

1. Tool Installer
2. How to install and work on the tool
3. NEXYS A7 Board and datasheet

Requirements

Please note that the tool we are going to use requires either
1. Windows 7,
2. Windows 10,
3. Linux, or Ubuntu.
If you have Windows 11, I recommend setting up dual boot on your system with one of the above operating systems.
Windows 10 is the best solution for this purpose. If you can set up a dual boot with Windows 10 and Windows 11 on your system, you can save Windows 11 and use Windows 10 with more than 50GB of space.
However, I strongly advise you to seek proper help from a network administrator or a computer shop professional if you are not familiar with the process.
They will charge no more than 300 rs. If you decide to do it on your own, make sure to back up your important files.

Audience

Pursuing Electricals and Electronics Engineering and Preparing for VLSI & Embedded

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