Hardware Design using Digital Components and Its Implementation on FPGA For SF 55
Foundation_Course_Digital_Hardware_Design_For_Electronics & Electricals_Engineering__2023_2024
Program objective of Project-based Learning cum Internship Program in VLSI: –
1. Understanding Hardware Design of VLSI & Embedded Domain
2. Hands-on Experience Design and
3. Optimization Techniques
4. Industry-Relevant Skills
5. Project Development
6. Networking and Industry Exposure
Summary of the program:-
1. Introduction of VLSI & Embedded flow
2. From this training, trainees can identify the interest area in VLSI & Embedded
3. 100% hands-on session from the first day of the learning
4. Focus on Major and minor project-based internship
5. From this training, students can identify their final-year project
6. Tools and Hardware board will be provided by the academy only
Key takeaways from the training program: –
1. How to develop the logical approach using digital components in hardware design and Implementation of FPGA
2. Hardware Circuit design using digital components of Real-time applications like signed calculator, multiplier,
divider, digital clock, stopwatch timer, and LED blinker.
3. Understanding of FPGA Architecture from Idea to programming in both hardware design and HDL- Verilog
What Will I Learn?
- 1. How to develop the logical approach using digital components in hardware design and Implementation of FPGA
- 2. Hardware Circuit design using digital components of Real-time applications like signed calculator, multiplier,
- divider, digital clock, stopwatch timer, and LED blinker.
- 3. Understanding of FPGA Architecture from Idea to programming in both hardware design and HDL- Verilog
What Will I Learn?
- 1. How to develop the logical approach using digital components in hardware design and Implementation of FPGA
- 2. Hardware Circuit design using digital components of Real-time applications like signed calculator, multiplier,
- divider, digital clock, stopwatch timer, and LED blinker.
- 3. Understanding of FPGA Architecture from Idea to programming in both hardware design and HDL- Verilog
Course Content
Combination
-
Gates and Self Design Gates
40:49 -
Adder
01:07:26 -
Digital L2 SFF 4th July 24
01:02:23 -
Digital L3 SFF 6th July 24
01:34:11 -
Digital L4 Sign Multiplier
01:18:07 -
Digital_L4_SFF_11th_July_24 Divider
01:31:36 -
Digital L4 SFF 12th July 24
58:57 -
Digital L4 SFF 16th July 24
01:20:39 -
Digital_L5_SFF_15th_July_24_MUX_A
57:07 -
Digital_L5_SFF_24th_July_24_MUX_B
01:18:35 -
Doubt Session SF _55_57_56_54
01:06:04 -
SF 57 Encoder Decoder Multiplier
01:46:26
Verilog Design
Sequential
About the instructor
9 Courses
375 students