STA & PNR Mentor @PinE

Industry experience of 12-year experience in VLSI Design and STA domain. He Has good exposure to EDA standard PnR and STA tools. Expertise in Floorplanning, placement, CTS, routing, congestion removal, LVS and DRC fix, LEC checks, etc. Experience in improving many timing failures. designs. Hands-on knowledge of all timing concepts. Working for enhancement of new technology and features added in STA tool.